CRAY-2 Reboot

The goal of this project is to make a clock and gate equivalent recreation of a Cray Research Cray-2 supercomputer that will run on an FPGA board. Resources permitting, a small IC run using MOSIS or CMP will be the stretch goal for the project. This project will be made of a number of phases:

1) Find documentation, code, etc. (This as expected is hard)
2) Conversion of module logic to working Verilog code - Complete (with the exception of the memory module)
3) Cleanup of Verilog code - 50% mark
4) Interconnecting all the Verilog together into a functional machine
5) Software emulation of the Verilog code for verification
6) Recovery and/or creation of basic OS & C compiler for the system (c complier will likely be a translated version of TCC)
7) Testing on FPGAs